发明名称 VOLTAGE LEVEL SHIFTERS EMPLOYING PRECONDITIONING CIRCUITS, AND RELATED SYSTEMS AND METHODS
摘要 Voltage level shifters employing preconditioning circuits are disclosed. Related systems and methods are also disclosed. In one aspect, voltage level shifter is configured to generate a voltage level shifted non-complement output signal and complement output signal corresponding to non-complement input signal and complement input signal, respectively. First pull-up circuit is configured to generate complement output signal in response to non-complement input signal transitioning to logic low voltage. First pull-down circuit is configured to generate non-complement output signal in response to complement input signal transitioning to logic high voltage. First preconditioning circuit is configured to receive non-complement and complement output signals and generate and provide shifted voltage signal to complement output in response to non-complement output signal transitioning to logic low voltage. This allows the complement output signal to transition to the shifted voltage more quickly.
申请公布号 US2016359487(A1) 申请公布日期 2016.12.08
申请号 US201514731747 申请日期 2015.06.05
申请人 QUALCOMM Incorporated 发明人 Nadkarni Rahul Krishnakumar;Liles Stephen Edward;Garg Manish
分类号 H03K19/0185 主分类号 H03K19/0185
代理机构 代理人
主权项 1. A voltage level shifter, comprising: a first pull-up circuit, comprising: a first input configured to receive a non-complement input signal; anda second input configured to receive a non-complement output signal;the first pull-up circuit configured to generate a complement output signal on a first pull-up output coupled to a complement output; a first pull-down circuit, comprising: a first input configured to receive a complement input signal;the first pull-down circuit configured to generate the non-complement output signal comprising a ground voltage signal on a first pull-down output coupled to a non-complement output; a first preconditioning circuit, comprising: a first input configured to receive the non-complement output signal; anda second input configured to receive the complement output signal;the first preconditioning circuit configured to generate a shifted voltage signal of the complement input signal on a first preconditioning output directly coupled to the complement output in response to the non-complement output signal transitioning to a logic low voltage; and a fourth preconditioning circuit, comprising: a first input configured to receive the complement output signal; anda second input configured to receive the non-complement output signal;the fourth preconditioning circuit configured to generate the ground voltage signal on a fourth preconditioning output directly coupled to the non-complement output in response to the complement output signal transitioning to a logic high voltage.
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