| 发明名称 |
INTEGRATION OF HYBRID GERMANIUM AND GROUP III-V CONTACT EPILAYER IN CMOS |
| 摘要 |
A trench contact epilayer in a semiconductor device is provided. Embodiments include forming trenches through an interlayer dielectric (ILD) over source/drain regions in NFET and PFET regions; depositing a conformal silicon nitride (SiN) layer over the ILD and in the trenches; removing the SiN layer in the PFET region; growing a germanium (Ge) epilayer over the source/drain regions in the PFET region; depositing metal over the ILD and in the trenches in the NFET and PFET regions; etching the metal in the NFET region to expose the conformal SiN layer; removing the SiN layer in the NFET region; growing a Group III-V epilayer over the source/drain regions in the NFET region; and depositing metal over the ILD and in the trenches in the NFET region. |
| 申请公布号 |
US2016358826(A1) |
申请公布日期 |
2016.12.08 |
| 申请号 |
US201514731480 |
申请日期 |
2015.06.05 |
| 申请人 |
GLOBALFOUNDRIES Inc. |
发明人 |
NIIMI Hiroaki;XIE Ruilong |
| 分类号 |
H01L21/8238;H01L21/31;H01L21/3205;H01L21/283;H01L29/45;H01L21/321;H01L29/78;H01L29/66;H01L29/417;H01L21/311;H01L21/3213 |
主分类号 |
H01L21/8238 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method comprising:
forming trenches through an interlayer dielectric (ILD) over source/drain regions in NFET and PFET regions; depositing a conformal silicon nitride (SiN) layer over the ILD and in the trenches; removing the SiN layer in the PFET region; growing a germanium (Ge) epilayer over the source/drain regions in the PFET region; depositing metal over the ILD and in the trenches in the NFET and PFET regions; etching the metal in the NFET region to expose the conformal SiN layer; removing the SiN layer in the NFET region; growing a Group III-V epilayer over the source/drain regions in the NFET region; and depositing metal over the ILD and in the trenches in the NFET region. |
| 地址 |
Grand Cayman KY |
