MINIMIZING SHORTING BETWEEN FINFET EPITAXIAL REGIONS

摘要

The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.

主权项

1. A method comprising:
forming a dummy gate layer on a first fin group and a second fin group; forming an opening in the dummy gate layer between the first fin group and the second fin group, the opening exposing an upper surface of a substrate; forming a dielectric region in the opening; forming a dummy gate aligned with the dielectric region, and covering a middle portion of the first fin group and a middle portion of the second fin group; and replacing the dummy gate with a gate structure.