METHODS AND APPARATUS FOR SIGNAL FLOW GRAPH PIPELINING IN AN ARRAY PROCESSING UNIT THAT REDUCES STORAGE OF TEMPORARY VARIABLES

摘要

A system for pipelining signal flow graphs by a plurality of shared memory processors organized in a 3D physical arrangement with the memory overlaid on the processor nodes that reduces storage of temporary variables. A group function formed by two or more instructions to specify two or more parts of the group function. A first instruction specifies a first part and specifies control information for a second instruction adjacent to the first instruction or at a pre-specified location relative to the first instruction. The first instruction when executed transfers the control information to a pending register and produces a result which is transferred to an operand input associated with the second instruction. The second instruction specifies a second part of the group function and when executed transfers the control information from the pending register to a second execution unit to adjust the second execution unit's operation on the received operand.

主权项

1. A method of executing a chain of instructions as part of a program executed by an array processing unit, the method comprising:
receiving a chain of instructions that includes a load instruction and, in the chain of instructions, a destination instruction having a dependency on the load instruction, wherein the load instruction identifies a first memory node, a fetch address of a first data operand in the first memory node, and a position of the destination instruction in the chain of instructions, and wherein the destination instruction identifies a function that takes the first data operand as an input; executing the load instruction to access the first data operand from the first memory node at the fetch address for delivery through a load network to a destination register included in a destination node associated with the position of the destination instruction, wherein according to a G×H matrix, a G×H array of memory nodes is connected by the load network to a G×H array of destination nodes, the load network comprising N-input by N-output multiplexing (N×N) elements organized into stages for corresponding dimensions of the G×H matrix, and in each stage having wiring configured according to a 1 to N adjacency of connections to the N×N elements which includes wrap around adjacent N×N elements and connections between memory nodes, N×N elements, and destination nodes in the same position in the G×H matrix, N an odd integer, N>1, G≧N and H≧N; and executing the destination instruction in the destination node to access the first data operand from the destination register, to input the accessed first data operand to the function specified by the destination instruction, and to produce a result for use in the program.