发明名称 |
METHOD OF MAKING A THREE-DIMENSIONAL MEMORY DEVICE HAVING A HETEROSTRUCTURE QUANTUM WELL CHANNEL |
摘要 |
A cylindrical confinement electron gas confined within a two-dimensional cylindrical region can be formed in a vertical semiconductor channel extending through a plurality of electrically conductive layers comprising control gate electrodes. A memory film in a memory opening is interposed between the vertical semiconductor channel and the electrically conductive layers. The vertical semiconductor channel includes a wider band gap semiconductor material and a narrow band gap semiconductor material. The cylindrical confinement electron gas is formed at an interface between the wider band gap semiconductor material and the narrow band gap semiconductor material. As a two-dimensional electron gas, the cylindrical confinement electron gas can provide high charge carrier mobility for the vertical semiconductor channel, which can be advantageously employed to provide higher performance for a three-dimensional memory device. |
申请公布号 |
US2016358933(A1) |
申请公布日期 |
2016.12.08 |
申请号 |
US201514733335 |
申请日期 |
2015.06.08 |
申请人 |
SANDISK TECHNOLOGIES INC. |
发明人 |
Rabkin Peter;Pachamuthu Jayavel;Alsmeier Johann;Higashitani Masaaki |
分类号 |
H01L27/115;H01L29/12;H01L29/45;H01L21/324;H01L21/28;H01L29/205;H01L21/02 |
主分类号 |
H01L27/115 |
代理机构 |
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代理人 |
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主权项 |
1. A method of forming a monolithic three-dimensional memory device, comprising:
forming a stack of alternating layers comprising first material layers and second material layers over a substrate; forming a memory opening through the stack of alternating layers; forming a memory film in the memory opening; forming a first semiconductor material layer having a first band gap over the memory film; and forming a second semiconductor material layer having a second band gap that is narrower than the first band gap over the first semiconductor material layer, wherein a heterostructure quantum well is formed at an interface between the first semiconductor material layer and the second semiconductor material layer. |
地址 |
PLANO TX US |