Method Of Forming Split Gate Memory Cells With 5 Volt Logic Devices

摘要

A method of forming a memory device on a semiconductor substrate having a memory region (with floating and control gates), a first logic region (with first logic gates) and a second logic region (with second logic gates). A first implantation forms the source regions adjacent the floating gates in the memory region, and the source and drain regions adjacent the first logic gates in the first logic region. A second implantation forms the source and drain regions adjacent the second logic gates in the second logic region. A third implantation forms the drain regions adjacent the control gates in the memory region, and enhances the source region in the memory region and the source/drain regions in the first logic region. A fourth implantation enhances the source/drain regions in the second logic region.

主权项

1. A method of forming a memory device, comprising:
providing a semiconductor substrate having a memory region, a first logic region and a second logic region; forming a pair of spaced apart floating gates in the memory region; forming a pair of control gates in the memory region, wherein each control gate has a first portion adjacent to one of the floating gates and a second portion that extends up and over one of the floating gates; forming a first logic gate in the first logic region; forming a second logic gate in the second logic region; forming a first photo resist that covers the second logic region and portions of the substrate adjacent to the control gates in the memory region, but not the first logic region and not a portion of the substrate between the pair of floating gates; performing a first implantation that forms a source region in the substrate between the pair of floating gates, a source region in the substrate adjacent a first side of the first logic gate, and a drain region in the substrate adjacent a second side of the first logic gate opposite the first side of the first logic gate; removing the first photo resist; forming a second photo resist that covers the first logic region and the memory region, but not the second logic region; performing a second implantation that forms a source region in the substrate adjacent a first side of the second logic gate and a drain region in the substrate adjacent a second side of the second logic gate opposite the first side of the second logic gate; removing the second photo resist; forming a third photo resist that covers the second logic region, but not the memory region and not the first logic region; performing a third implantation that forms drain regions in the substrate adjacent the control gates; removing the third photo resist.