Speculative Load Data in Byte-Write Capable Register File and History Buffer for a Multi-Slice Microprocessor

摘要

An approach is provided is provided in which a computing system matches a writeback instruction tag (ITAG) to an entry instruction tag (ITAG) included in an issue queue entry. The writeback ITAG is provided by a first of multiple load store units. The issue queue entry includes multiple ready bits, each of which corresponds to one of the multiple load store units. In response to matching the writeback ITAG to the entry ITAG, the computer system sets a first ready bit corresponding to the first load store unit. In turn, the computing system issues an instruction corresponding to the entry ITAG based upon detecting that each of the multiple ready bits is set.

主权项

1. (canceled)