| 摘要 |
Multi-threaded processing using the processing 5 pipeline 6, 8, 10, 12, 14, 16, 18 uses flush control circuitry 30 responsive to multiple different types of flush trigger. Different types of flush trigger result in different sets of state being flushed for the thread which resulted in the flush trigger with state for other thread not being flushed. For example, a relatively low latency stall may result in flushing back to a first flush point, whereas a longer latency stall results in flushing back to a second flush point and the loss of more state data, such as a cache miss and a division / square root operation. The 10 data flushed back to the first flushed point may be a proper subset of the data flushed back to the second flush point. This allows additional processing of other thread(s), and use a hierarchical memory so that a first flush trigger corresponds to a first cache, memory level. |
