Asymmetry detection apparatus, jitter detection apparatus, and recording/reproduction apparatus

摘要

An asymmetry detection apparatus includes: a clock signal generator for generating a clock signal based on a reproduced signal; an A/D converter for sampling the reproduced signal in synchronization with the clock signal; a determiner for determining whether a level of each of a plurality of sampled data obtained by the sampling operation is equal to or greater than a predetermined level; and a detector for detecting asymmetry in the reproduced signal by using predetermined ones of the sampled data based on an output from the determiner. A jitter detection apparatus includes: a clock signal generator for generating a clock signal based on a reproduced signal; an A/D converter for sampling the reproduced signal in synchronization with the clock signal; a determiner for determining whether a level of each of a plurality of sampled data obtained by the sampling operation is equal to or greater than a predetermined level; and a detector for detecting jitter in the reproduced signal by using predetermined ones of the plurality of sampled data based on an output from the determiner.