发明名称 半導体装置の製造方法
摘要 PROBLEM TO BE SOLVED: To reduce a time necessary for confirmation of electrical conduction between a probe and a via.SOLUTION: A semiconductor device manufacturing method comprises: a process of bringing a probe in contact with a via connected to a gate which is not electrically connected with a substrate on which a source, a drain and the gate are formed; a process of applying a DC pulse voltage to the gate to measure electrical characteristics; and a process of determining whether the probe and the via connected to the gate are electrically conductive based on the measured electrical characteristics.
申请公布号 JP6040815(B2) 申请公布日期 2016.12.07
申请号 JP20130055732 申请日期 2013.03.18
申请人 富士通株式会社 发明人 澤井 暢大
分类号 H01L21/66;G01R31/28 主分类号 H01L21/66
代理机构 代理人
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