发明名称 High efficiency quasi-vertical DMOS in MOS or BICMOS process
摘要 A QVDMOS array 10 has QVDMOS devices with a silicide contact 42 to source 35 and body tie 36. The body tie 36 is enclosed by the source at the surface and extends beneath but not beyond the annular source 35. The QVDMOS is formed during a number of process steps that simultaneously form regions in NMOS, PMOS and bipolar devices. <IMAGE>
申请公布号 EP0747966(B1) 申请公布日期 2002.01.02
申请号 EP19960107796 申请日期 1996.05.15
申请人 HARRIS CORPORATION 发明人 PEARCE, LAWRENCE G.
分类号 H01L27/06;H01L29/06;H01L29/10;H01L29/417;H01L29/45;H01L29/78 主分类号 H01L27/06
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