| 摘要 |
A multiprocessor device includes a plurality of cache devices connected to a plurality of processors respectively, a consistency control unit connected to the plurality of cache devices, and a main memory. The cache device caches data accessed by a processor connected to the cache device, manages the cached data on the basis of a memory block. When the consistency control unit issues a write back request of a memory block, the cache device transmits the memory block to the consistency control unit. The consistency control unit merges data in the memory block supplied from the cache and the merged memory block is stored in the main memory.
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