发明名称 PHASE CONTROLLER AND METHOD THEREFOR
摘要 PROBLEM TO BE SOLVED: To provide a phase controller capable of matching clock phases between plural blocks in a short time by combining a counter method and a binary search method. SOLUTION: This phase controller is provided with a comparison means 100 for comparing a first clock and a second clock and outputting comparison signals, a counter means 200 for adjusting the delay of an output clock with first delay time as a unit by the comparison signals 100, outputting operation signals at the time of exceeding the adjustable time of the delay and outputting the output clock when the phases are matched within the adjustable time of the delay and a binary search means 300 for adjusting the delay of the output clock by second delay time longer than the first delay time by using binary search by the comparison signals 100 and performing output to the counter means when the operation signals are inputted.
申请公布号 JPH11205128(A) 申请公布日期 1999.07.30
申请号 JP19980006043 申请日期 1998.01.14
申请人 TOSHIBA MICROELECTRONICS CORP;TOSHIBA CORP 发明人 HOSOYA KAZUHIKO;FUJII OSAMU
分类号 G06F1/08;H03K5/26;H03L7/00 主分类号 G06F1/08
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