CLOCK SYNCHRONIZATION DELAY CONTROL CIRCUIT

摘要

PROBLEM TO BE SOLVED: To accelerate the operation of a synchronous type LSI by reducing the time needed to synchronize an external and an internal clock with each other. SOLUTION: A pulse having pulse widthαnarrower than the duty of an external clock is generated by a pulse generating circuit 3, delayed by a delay monitor 5, and then transmitted to a time-to-digital converter 6 and a digital-to- time converter 7. The delay time accompanying the input and output of the clock is compensated by those delay monitor 5 and converters 6 and 7. The pulse widthαof the pulse outputted by being transmitted through the converters 6 and 7 is restored by a pulse width restoring circuit 8 to the pulse width of the internal clock.