Method for checking and fixing double-patterning layout

摘要

A method includes receiving layout data representing a plurality of patterns. The layout data includes a plurality of layers and spaces identified between adjacent patterns. In at least one layer of the plurality of layers, the adjacent patterns violate a G0-rule. The method further includes determining whether each identified space is a critical G0-space. The identified space is determined to be a critical G0-space if a portion of at least one adjacent pattern that is removed merges two adjacent odd-loops of G0-spaces into a single even loop or G0 spaces or alternatively, if a portion of an adjacent pattern that is removed converts one odd-loop of G0-spaces to a non-loop of G0-spaces. The method further includes receiving a modification of at least one adjacent pattern and updating a spacing of a layer that is adjacent to the layers within the adjacent pattern that violate the G0-rule.

主权项

1. A circuit layout method of forming two masks for a plurality of patterns, said method comprising:
receiving layout data representing the plurality of patterns, the layout data including a plurality of layers; identifying, by a processor of a computer system, spaces between adjacent patterns in at least one layer of the plurality of layers which violate a G0-rule; determining whether each identified space is a critical G0-space, by the processor, wherein the identified space is determined to be the critical G0-space if removal of a portion of at least one pattern merges two adjacent odd-loops of G0-spaces into a single even-loop of G0-spaces or converts one odd-loop of G0-spaces to a non-loop of G0-spaces; performing an adjustment, using the processor, of the at least one pattern based on a determination that at least one space is the critical G0-space based on received instructions; and outputting an adjusted representation of the plurality of patterns, the adjusted representation including identified G0-rule violations and determined critical G0 spaces.