| 摘要 |
PROBLEM TO BE SOLVED: To provide the multiplier circuit configured with a digital circuit, that corresponds to a frequency of an optional reference input signal by controlling number of delay elements of a delay circuit so as to adjust the delay. SOLUTION: A delay circuit 1 receives a reference input signal ref and provides an output to a selection circuit 4. A phase comparator 2 receives a reference input signal ref and an output DO of the selection circuit 4 and provides an output to an up-down counter 3. The selection circuit 4 receives an output of the up-down counter 3 and an N multiple setting input signal IN provides an output to the phase comparator 2 and to an exclusive OR circuit 5. A delay in the input signal is adjusted, a delay by a phase difference desired to be delayed with respect to the reference input signal is set based on the adjusted delay, the reference input signal and a plurality of phase delay signals are given to the exclusive OR circuit 5, from which a signal with a higher frequency than that of the reference signal is outputted. Since an LPF hardly susceptible to the effect of power noise is not required, the multiplier circuit with ease of design is obtained. |
