Controlling power gate circuitry based on dynamic capacitance of a circuit

摘要

In one embodiment, the present invention includes an apparatus having an estimation logic to estimate a dynamic capacitance of a processor circuit of a processor during a plurality of processor cycles, a power gate calculator to calculate a control value for a power gate circuit coupled to a load line and between a voltage regulator and the processor circuit based on the dynamic capacitance estimate, and a controller to control an impedance of the power gate circuit based on the control value. Other embodiments are described and claimed.

主权项

1. A processor comprising:
an estimation logic to estimate a dynamic capacitance of a first processor circuit of the processor during a first plurality of processor cycles, wherein the dynamic capacitance estimate comprises a ratio between the dynamic capacitance estimate of the first processor circuit during the first plurality of processor cycles and a dynamic capacitance of the first processor circuit during execution of a power virus; a power gate calculator to calculate a control value for a power gate circuit coupled to a load line and between a voltage regulator and the first processor circuit based on the dynamic capacitance estimate, wherein the control value is to control a width of the power gate circuit; and a controller to control an impedance of the power gate circuit based on the control value to absorb an over-voltage.