发明名称 Multi-die fine grain integrated voltage regulation
摘要 A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used.
申请公布号 US9595526(B2) 申请公布日期 2017.03.14
申请号 US201314077512 申请日期 2013.11.12
申请人 Apple Inc. 发明人 Zerbe Jared L.;Fang Emerson S.;Zhai Jun;Searles Shawn
分类号 H01L21/02;H01L27/10;H01L23/48;H01L23/13;H01L23/64;H01L25/16;H01L25/18;H01G4/228;H01L49/02;H01L23/00;H01L25/065;H01L25/10;H01L23/498;H01L23/50 主分类号 H01L21/02
代理机构 Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C. 代理人 Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C. ;Sampson Gareth M.;Merkel Lawrence J.
主权项 1. A semiconductor device, comprising: a semiconductor substrate; a plurality of passive structures formed into an array on a surface of the semiconductor substrate, wherein the passive structures comprise one or more passive elements formed on the semiconductor substrate, at least one of the passive elements being a capacitor, and wherein the array comprises a regular array in x- and y-directions on the surface of the semiconductor substrate, the regular array in x- and y-directions comprising at least two capacitors arrayed in the x-direction and at least two capacitors arrayed in the y-direction; and a plurality of terminals on the surface of the semiconductor substrate for coupling the array of passive structures to at least one additional semiconductor device; wherein the array comprises a tiled pattern of the passive structures, and wherein each tile includes at least two of the plurality of terminals on the surface of the semiconductor substrate distinctly associated with the passive elements in the tile, and wherein a first terminal distinctly associated with the passive elements in the tile comprises an anode for the passive elements in the tile and a second terminal distinctly associated with the passive elements in the tile comprises a cathode for the passive elements.
地址 Cupertino CA US