Chip substrate comprising a plated layer and chip package using the same

摘要

A chip substrate includes laminated conductive portions, and laminated insulation portions that electrically isolate the conductive portions, with a cavity in a recessed shape in a region including the insulation portions on an upper surface of the chip substrate. The substrate includes an insulation layer on the upper surface, excluding a region of the cavity, and a continuous plating layer along a periphery of the chip substrate on the insulation layer. A portion of a top surface of each insulation portion is exposed in the cavity, and another portion of the top surface of each insulation portion is coated with the insulation layer. A chip package includes a chip substrate, with an optical element sealed in the cavity by a sealing member or lens.

主权项

1. A chip substrate, comprising:
conductive portions laminated in one direction to constitute the chip substrate; insulation portions vertically penetrating the conductive portions to electrically isolate the conductive portions; a cavity formed at a predetermined depth in a recessed shape in a region including the insulation portions on an upper surface of the chip substrate; an insulation layer coated on an upper surface of the chip substrate excluding a region of the cavity; and a plating layer continuously formed at a predetermined width along a periphery of the chip substrate on the insulation layer, wherein a portion of a top surface of each insulation portion is exposed in the cavity, and another portion of the top surface of each insulation portion is coated with the insulation layer.