Device for generating test pattern

摘要

A device that is capable of generating a new test pattern after the design phase and has a small area of a circuit not in use during normal operation includes a first circuit and a second circuit. The second circuit includes a third circuit and fourth circuit. The fourth circuit has a function of storing data for determining the configuration of the third circuit. When a test for the operating state of the first circuit is performed, the second circuit has a function of generating a signal for the test. When the test is not performed, the second circuit has a function of storing data used for processing in the first circuit and a function of comparing a plurality of signals.

主权项

1. A device comprising:
a first circuit; and a second circuit, wherein the first circuit comprises a first memory, wherein the first memory is configured to store first data corresponding to a first address of a first instruction of the first circuit, wherein the second circuit comprises a second memory, a third memory, a fourth memory, and a fifth memory, wherein the second memory is configured to store second data to generate a signal for an operation test of the first circuit, and configured to store third data corresponding to a second address of a second instruction of the first circuit after the operation test, wherein the third memory is configured to store fifth data to generate the signal for the operation test of the first circuit, and configured to store inverted data of the third data after the operation test, wherein the fourth memory is configured to store sixth data to generate the signal for the operation test of the first circuit, and configured to store seventh data corresponding to a third address of a third instruction of the first circuit after the operation test, wherein the fifth memory is configured to store eighth data to generate the signal for the operation test of the first circuit, and configured to store inverted data of the seventh data after the operation test, wherein the second circuit is configured to compare the third data and fourth data corresponding to a fourth address of a fourth instruction of the first circuit after the operation test, and wherein the second circuit is configured to compare the seventh data and the fourth data corresponding to the fourth address of the fourth instruction of the first circuit after the operation test.