| 摘要 |
PROBLEM TO BE SOLVED: To attain a high tuning speed by reducing a lockup time. SOLUTION: A frequency divider 15 outputs a signal fp1 obtained by frequency-dividing a frequency signal fv and a frequency divider 18 outputs a signal fp2 obtained by frequency-dividing a signal S1 with a same frequency division ratio as that of the frequency divider 15. A lock detector 23 detects a phase lock of signals fr, fp2 based on a reference signal fr and the signal fp2 to outputs a signal LD. A multiplexer 24 selects the signal fp1 or fp2 based on the signal LD and outputs the selected signal as a signal fp. A phase comparator 21 outputs phase difference signalsϕR,ϕP based on the signals fr, fp and a C/P circuit 25 outputs a voltage signal D0 based on the signalsϕR,ϕP. A voltage controlled oscillator(VCO) 27 outputs a signal fv in response to a voltage of a control voltage signal VT. A phase comparator 22 outputs a phase difference signalϕP1 based on the phase difference of the signals fr, fp. An AND circuit 28 is a circuit to give the signal fv to the frequency divider 18 and invalidates the signal fv for a time when the signalϕP1 is outputted.
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