Nonvolatile semiconductor memory device

摘要

When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

主权项

1. A memory device, comprising
a memory cell array including a first block, the first block including a first group and a second group, the first group including a first unit and a second unit, the second group including a third unit and a fourth unit, a gate of a drain side selection transistor in the first unit being coupled to a gate of a drain side selection transistor in the second unit, a gate of a drain side selection transistor in the third unit being coupled to a gate of a drain side selection transistor in the fourth unit, gates of memory cells in the first to third unit being coupled to a gate of a memory cell in the fourth unit, wherein the memory device is capable of selectively erasing data stored in either the first group or the second group.