Design-for-test apparatuses and techniques

摘要

Embodiments of design-for-test (DFT) apparatuses and related techniques are disclosed herein. In some embodiments, a DFT apparatus may include an SRAM cell, read/write (R/W) circuitry to provide a nominal word line (WL) voltage and a nominal BL voltage for application to the SRAM cell during accesses. The DFT apparatus may also include test circuitry having an activated state and a deactivated state. When the test circuitry is in the activated state, in some embodiments, the WL voltage and/or the BL voltage applied to the SRAM cell may be different from the nominal voltages provided by the R/W/decoder circuitry. The R/W/decoder circuitry may be operated to perform accesses to the SRAM cell while the test circuitry is in the activated state. Other embodiments may be disclosed and/or claimed.

主权项

1. An apparatus, comprising:
a static random access memory (SRAM) cell comprising a word line (WL) to receive an applied WL voltage and a bit line (BL) to receive an applied BL voltage; read/write/decoder circuitry to selectively provide first and second WL voltages for application to the WL, and selectively provide first and second BL voltages for application to the BL, wherein the first WL voltage is greater than the second WL voltage and the first BL voltage is greater than the second BL voltage; and test circuitry coupled to the SRAM cell and the read/write/decoder circuitry, the test circuitry having an activated state and a deactivated state, wherein, when the test circuitry is in the activated state, the read/write/decoder circuitry is to simulate operation of the SRAM cell under low temperature conditions that are less than approximately 25 degrees Celsius.