发明名称 |
Estimating scalability value for a specific domain of a multicore processor based on active state residency of the domain, stall duration of the domain, memory bandwidth of the domain, and a plurality of coefficients based on a workload to execute on the domain |
摘要 |
In an embodiment, a processor includes a first logic to calculate a scalability value for a processor domain based at least in part on an active state residency, a stall duration, and a memory bandwidth of the domain, and to determine an operating frequency update for the domain based at least in part on a current operating frequency of the domain and the scalability value. Other embodiments are described and claimed. |
申请公布号 |
US9594560(B2) |
申请公布日期 |
2017.03.14 |
申请号 |
US201314039151 |
申请日期 |
2013.09.27 |
申请人 |
Intel Corporation |
发明人 |
Ananthakrishnan Avinash N.;Gunther Stephen H.;Shrall Jeremy J.;Schwartz Jay D. |
分类号 |
G06F1/00;G06F9/30;G06F11/34;G06F12/08;G06F9/48;G06F1/32 |
主分类号 |
G06F1/00 |
代理机构 |
Trop, Pruner & Hu, P.C. |
代理人 |
Trop, Pruner & Hu, P.C. |
主权项 |
1. A processor comprising:
a first logic to calculate a scalability value for a domain of the processor based at least in part on an active state residency of the domain, a stall duration of the domain and memory bandwidth information of the domain, and to determine an operating frequency update for the domain based on a current operating frequency of the domain and the scalability value, wherein the domain includes an active state residency counter to count a number of cycles of an evaluation time interval in which the domain is in an active state, a stall counter to count a number of cycles of the evaluation time interval in which the domain is in a stall state in which execution units of the domain are waiting for a memory transaction to complete to make forward progress and a plurality of memory bandwidth counters to count a number of transactions between the domain and a system memory coupled to the processor, the first logic to determine the active state residency based on a value of the active state residency counter and to determine the stall duration based on a value of the stall counter, and to calculate the scalability value according to:
(A*C0_residency_time+B*memory_stalled_time+C*memory_read_bandwidth+D*memory_write_bandwidth)/C0_residency_time,wherein C0_residency_time is a value of the active state residency counter, memory_stalled_time is a value of the stall counter, memory_read_bandwidth and memory_write_bandwidth are values of the plurality of memory bandwidth counters and A, B, C and D are coefficients selected based on a workload executed in the processor. |
地址 |
Santa Clara CA US |