| 摘要 |
According to one embodiment, a semiconductor memory 100 includes a memory cell array 100A composed of a plurality of SRAM cells 10 including NMOS transistors and PMOS transistors, and a bias circuit 100B connected to a ground GND1 or power supply voltage VDD1 of the memory cell array 100A. The bias circuit 100B includes NMOS transistors 121, 122, 133 and 134 that are same as the NMOS transistors of the SRAM cells 10 in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion, and PMOS transistors 111 and 112 that are same as the PMOS transistors of the SRAM cells 10 in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion. Diffusion regions of the NMOS transistors and the PMOS transistors are formed in a same semiconductor layer. |
| 主权项 |
1. A semiconductor memory comprising:
a memory cell array composed of a plurality of SRAM cells, one of which includes a first NMOS transistor and a first PMOS transistor; and a bias circuit connected to a first ground line or a power supply voltage line of the memory cell array, wherein the bias circuit includes a second NMOS transistor that is same as the first NMOS transistor in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion, and a second PMOS transistor that is same as the first PMOS transistor in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion, diffusion regions of the first and second NMOS transistors and diffusion regions of the first and second PMOS transistors are formed in a same semiconductor layer, the bias circuit includes one or more bias cells, one of the one or more bias cells includes four transistors that constitute two inverters cross-connected to each other, and two transistors that constitute transfer gates for performing readout and write, and the NMOS transistor and the PMOS transistor correspond to one or more of the four transistors that constitute the two inverters and the two transistors that constitute the transfer gates. |
