SEMICONDUCTOR MEMORY DEVICE

摘要

A semiconductor memory device includes a substrate, a plurality of first control gate electrodes, a plurality of second control gate electrodes, first to second select gate electrodes, first to second gate electrodes, a bit line, first to second semiconductor pillars, and a controller. The controller applies a first potential to the first select gate electrode, a third potential lower than the first potential to the second select gate electrode, a second potential to the first gate electrode and the second gate electrode, a selecting potential not less than the third potential to one of the plurality of the first control gate electrodes, and an unselecting potential higher than the selecting potential to other than the one of the plurality of first control gate electrodes in a reading operation.

主权项

1. A semiconductor memory device comprising:
a substrate; a plurality of first control gate electrodes stacked along a first direction above the substrate; a plurality of second control gate electrodes stacked along the first direction above the substrate, the plurality of second control gate electrodes being arranged with the plurality of first control gate electrodes in a second direction intersecting the first direction; a first select gate electrode provided above the plurality of first control gate electrodes; a second select gate electrode provided above the plurality of second control gate electrodes; a first gate electrode provided above the first select gate electrode; a second gate electrode provided above the second select gate electrode; a bit line provided above the first gate electrode and the second gate electrode, the bit line extending in the second direction; a first semiconductor pillar piercing the plurality of first control gate electrodes, the first select gate electrode and the first gate electrode in the first direction and electrically connected to the bit line; a second semiconductor pillar piercing the plurality of second control gate electrodes, the second select gate electrode and the second gate electrode in the first direction and electrically connected to the bit line; and a controller configured to apply a first potential to the first select gate electrode, a third potential lower than the first potential to the second select gate electrode, a second potential to the first and second gate electrodes, a selecting potential not less than the third potential to one of the plurality of first control gate electrodes, and an unselecting potential higher than the selecting potential to other than the one of the plurality of first control gate electrodes in a reading operation.