| 发明名称 |
CMOS DEVICE WITH DECREASED LEAKAGE CURRENT AND METHOD MAKING SAME |
| 摘要 |
A complementary metal oxide semiconductor (CMOS) device includes a p-channel metal oxide semiconductor (PMOS) transistor unit and an n-channel metal oxide semiconductor (NMOS) transistor unit. A semiconductor layer of the PMOS transistor unit between source and drain electrodes thereof is divided into a first tapered region having an ion concentration of CP/e and a first flat region having an ion concentration of CP/f. A semiconductor layer of the NMOS transistor unit between source and drain electrodes thereof is divided into a second tapered region having an ion concentration of CN/e, a second flat region having an ion concentration of CN/f−2 and a third flat region located between the second tapered region and second flat region and having an ion concentration of CN/f−1, wherein the ion concentrations have a relationship of CP/e<CP/f<CN/f−2<CN/e<CN/f−1. |
| 申请公布号 |
US2017069542(A1) |
申请公布日期 |
2017.03.09 |
| 申请号 |
US201514855626 |
申请日期 |
2015.09.16 |
| 申请人 |
HON HAI PRECISION INDUSTRY CO., LTD. |
发明人 |
KENJI ANJO |
| 分类号 |
H01L21/8238;H01L27/092;H01L29/16;H01L29/167;H01L29/66;H01L29/04 |
主分类号 |
H01L21/8238 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A complementary metal oxide semiconductor (CMOS) device comprising:
a p-channel metal oxide semiconductor (PMOS) transistor unit comprising a first source electrode, a first drain electrode, and a first semiconductor layer between the first source electrode and second drain electrode; a n-channel metal oxide semiconductor (NMOS) transistor unit comprising a second source electrode, a second drain electrode, and a second semiconductor layer between the second source electrode and second drain electrode; and at least one gate electrode for controlling operations of at least one of the PMOS transistor unit and the NMOS transistor unit, wherein the first semiconductor layer comprises a first tapered region having an ion concentration of CP/e and a first flat region having an ion concentration of CP/f; the second semiconductor layer has a second tapered region having an ion concentration of CN/e, a second flat region having an ion concentration of CN/f−2, and a third flat region having an ion concentration of CN/f−1 and located between the second tapered region and the second flat region; wherein a cross-section of the second tapered region is triangular; and the ion concentrations have following relationship: CP/e<CP/f<CN/f−2<CN/e<CN/f−1. |
| 地址 |
New Taipei TW |
