| 发明名称 |
SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM |
| 摘要 |
A semiconductor memory device includes a memory cell transistor and a word line connected a gate of the memory cell transistor. A first erase voltage is applied to the memory cell transistor when an erasing operation of a first type is performed on the memory cell transistor, and a second erase voltage, lower than the first erase voltage, is applied to the memory cell transistor when an erasing operation of a second type is performed on the memory cell transistor. |
| 申请公布号 |
US2017069372(A1) |
申请公布日期 |
2017.03.09 |
| 申请号 |
US201615193586 |
申请日期 |
2016.06.27 |
| 申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
KODAMA Erika;IWAI Hitoshi |
| 分类号 |
G11C11/56;G11C16/08;H01L27/115;G11C16/04 |
主分类号 |
G11C11/56 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A semiconductor memory device comprising:
a memory cell transistor; and a word line that is connected to a gate of the memory cell transistor, wherein an erase voltage of a first level is applied to the memory cell transistor when an erasing operation of a first type is performed on the memory cell transistor, and an erase voltage of a second level, which is lower than the first level, is applied to the memory cell transistor when an erasing operation of a second type is performed on the memory cell transistor. |
| 地址 |
Tokyo JP |
