发明名称 MAGNETIC RAM ARRAY ARCHITECTURE
摘要 A magnetic random access memory (MRAM) array including: a plurality of MRAM cells arranged in an array configuration, each comprising a first type nTron and a magnetic memory element; a wordline select circuit comprising of a second type nTron to drive a plurality of parallel wordlines; and a plurality of bitline select circuits, each comprising of said second type nTron for writing to and reading from a column of memory cells in the array and each capable of selecting a single MRAM cell for a memory read or write operation, wherein the second nTron has a higher current drive than the first nTron.
申请公布号 US2017069367(A1) 申请公布日期 2017.03.09
申请号 US201615356117 申请日期 2016.11.18
申请人 RAYTHEON BBN TECHNOLOGIES CORP. ;HYPRES, INC. 发明人 Ohki Thomas;Mukhanov Oleg;Kirichenko Alex
分类号 G11C11/16;G11C11/18 主分类号 G11C11/16
代理机构 代理人
主权项 1. A method for writing to and reading from a magnetic random access memory (MRAM) array, each memory cell in the array comprising of a memory cell select nTron (SnT) and a memory element, the method comprising: selecting a memory cell of the MRAM array by driving a word line and a bit line by a line select nTron (LnT), wherein the LnT has a higher current drive than the SnT; performing a memory write operation to a single MRAM cell by applying an nTron signal at a gate of the SnT of the single MRAM cell to switch the SnT to a resistive state; and performing a memory read operation from a single MRAM cell by applying a Single Flux Quantum (SFQ) signal at a gate of the SnT of the single MRAM cell to switch the SnT to a resistive state, applying a current to the memory element smaller than a critical current of the memory element to keep the memory element at its current state while being read, and sensing the voltage at the memory element to determine the resistive state of the memory element.
地址 Cambridge MA US