发明名称 MEMORY SYSTEM
摘要 According to one embodiment, a memory system includes a first volatile memory, a nonvolatile memory and a controller. The nonvolatile memory includes a plurality of chips. The controller generates a second error correcting code using data stored in the first volatile memory. The second error correcting code is a code for correcting data which cannot be corrected included in a first data group using a first error correcting code. The controller releases an area of the first volatile memory corresponding to the first data group written in the nonvolatile memory, before completion of writing of all of the data which are stored in the first volatile memory and includes in a codeword of the second error correcting code to the nonvolatile memory.
申请公布号 US2017070241(A1) 申请公布日期 2017.03.09
申请号 US201615067958 申请日期 2016.03.11
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 KAKU Erika;Kojima Yoshihisa
分类号 H03M13/29;G11C29/52;G06F11/10 主分类号 H03M13/29
代理机构 代理人
主权项 1. A memory system comprising: a first volatile memory configured to store data; a nonvolatile memory comprising a plurality of chips, the data stored in the first volatile memory being written to each of the chips for first data group, the first data group including a first error correcting code for correcting an error in the data; and a controller configured to control the first volatile memory and the nonvolatile memory, wherein the controller generates a second error correcting code using the data stored in the first volatile memory, the second error correcting code being a code for correcting data which cannot be corrected included in the first data group using the first error correcting code, and releases an area of the first volatile memory corresponding to the first data group written in the nonvolatile memory, before completion of writing of all of the data which are stored in the first volatile memory and includes a codeword of the second error correcting code to the nonvolatile memory.
地址 Minato-ku JP