PSEUDO RESISTANCE CIRCUIT AND CHARGE DETECTION CIRCUIT

摘要

A pseudo resistance circuit includes a first gate voltage adjustment circuit that adjusts respective currents of first and second current sources and also adjusts a gate voltage of a second field effect transistor to equalize or substantially equalize a drain voltage of the second field effect transistor and a voltage of a first end portion of a reference resistance element and controls a drain voltage of a first field effect transistor and the drain voltage of the second field effect transistor to maintain a constant or substantially constant relationship with each other; and a second gate voltage adjustment circuit that adjusts a gate voltage of the first field effect transistor to control the gate voltage of the second field effect transistor and the gate voltage of the first field effect transistor to maintain a constant or substantially constant relationship with each other.

主权项

1. A pseudo resistance circuit comprising:
a first current source; a second current source; a first field effect transistor that operates in a weak inversion region; a second field effect transistor including electrical characteristics matched or substantially matched to electrical characteristics of the first field effect transistor, a source terminal electrically connected to a reference voltage terminal, and a drain terminal electrically connected to the first current source; a reference resistance element including a first end portion electrically connected to the reference voltage terminal and a second end portion electrically connected to the second current source; a first gate voltage adjustment circuit that adjusts a current of the first current source and a current of the second current source and also adjusts a gate voltage of the second field effect transistor, to equalize or substantially equalize a drain voltage of the second field effect transistor and a voltage of the second end portion of the reference resistance element and controls a drain voltage of the first field effect transistor and the drain voltage of the second field effect transistor to maintain a constant or substantially constant relationship with each other; and a second gate voltage adjustment circuit that adjusts a gate voltage of the first field effect transistor to control the gate voltage of the first field effect transistor and the gate voltage of the second field effect transistor to maintain a constant or substantially constant relationship with each other.