CIRCUIT DESIGN DEVICE AND CIRCUIT DESIGN PROGRAM

摘要

A delay time calculation unit calculates a delay time required to execute a computation path when an error countermeasure step is inserted into the computation path per computation path included in a scheduled CDFG file. An inserted graph selection unit selects a computation path for which the delay time does not exceed a target time as inserted graph. An error countermeasure insertion unit inserts an error countermeasure notation indicating the error countermeasure step into the inserted graph.

主权项

1. A circuit design device comprising:
a divided graph acquisition unit to acquire a plurality of divided graphs generated by dividing a control data flow graph indicating a control data flow of an integrated circuit; an execution time calculation unit to calculate an execution time required to execute a division flow when an error countermeasure step is inserted into the division flow indicated by a divided graph per divided graph among the plurality of divided graphs; an inserted graph selection unit to select a divided graph for which the execution time does not exceed a target time, as inserted graph, from among the plurality of divided graphs based on each execution time calculated by the execution time calculation unit; and an error countermeasure insertion unit to insert an error countermeasure notation indicating the error countermeasure step into the inserted graph selected by the inserted graph selection unit.