SAMPLING IMPLEMENTATION METHOD AND DEVICE BASED ON CONVENTIONAL SAMPLING GOOSE TRIP MODE

摘要

Sampling implementation method and device based on conventional sampling GOOSE trip mode. CPU of master NPI plug-in, after receiving a second pulse, transmits sampling pulse generation time and a transmission enable bit to FPGA of the master NPI plug-in at a fixed interval; after detecting the transmission enable bit, the FPGA of the master NPI plug-in judges whether time of its internal timer is greater than/equal to the sampling pulse generation time, if yes, generates a sampling pulse to FPGA of collection plug-in; after receiving sampling pulse, the collection plug-in carries out A/D sampling, and transmits sampled data to the master NPI plug-in; when detecting that all A/D samplings are completed, the master NPI plug-in transmits data packets to protection CPU plug-in. The device includes an MMI plug-in, a protection CPU plug-in, a master NPI plug-in and a collection plug-in. Protection maloperation is thereby reduced.

主权项

1. A sampling implementation method based on a conventional sampling Generic Object Oriented Substation Events (GOOSE) trip mode, comprising:
1) transmitting, by a Central Processing Unit (CPU) of a master New Process layer Interface (NPI) plug-in after receiving a second pulse, sampling pulse generation time and a transmission enable bit to a Field Programmable Gate Array (FPGA) of the master NPI plug-in at a fixed interval; 2) judging, by the FPGA of the master NPI plug-in after detecting the transmission enable bit, whether time of an internal timer of the FPGA of the master NPI plug-in is greater than or equal to the sampling pulse generation time, if more than or equal to, generating a sampling pulse to an FPGA of a collection plug-in, and at the same time resetting the transmission enable bit; 3) carrying out Analog-to-Digital (A/D) sampling by the collection plug-in after receiving the sampling pulse of master NPI plug-in, and packing sampled data and transmitting data packets to the master NPI plug-in; 4) transmitting, by the FPGA of the master NPI plug-in when detecting that all the A/D samplings are completed, a sampling completion identifier to the CPU unit of the master NPI plug-in, and transmitting the data packets to a protection CPU plug-in for logical judgment.