发明名称 INPUT BUFFER WITH SELECTABLE HYSTERESIS AND SPEED
摘要 A buffer provides a signal at an output node as a function of an input signal. First and second buffer stages have respective current conduction paths for asserting the output signal. An enabling element selectively enables the second buffer stage in response to assertion of an enabling signal in a state where the first and second buffer stages are both simultaneously enabled. The first buffer stage has hysteresis feedback paths from the output node for providing hysteresis in the buffer response. The hysteresis is smaller when the first and second buffer stages are both enabled than when only the first buffer stage is enabled. The response of the second buffer stage to the input signal, when enabled, is faster than the first buffer stage.
申请公布号 US2017070213(A1) 申请公布日期 2017.03.09
申请号 US201615235074 申请日期 2016.08.11
申请人 FREESCALE SEMICONDUCTOR, INC. 发明人 ZHAO YI;Zhang Dongling
分类号 H03K3/012;H03K3/3565 主分类号 H03K3/012
代理机构 代理人
主权项 1. A buffer for providing a buffer output signal as a function of a first signal at a first node from an external source, the buffer comprising: first and second buffer stages having respective current conduction paths for asserting a second signal at a second node as a function of the first signal; and a first enabling element for selectively enabling the second buffer stage in response to assertion of a first enabling signal in a state where the first and second buffer stages are both simultaneously enabled; wherein the first buffer stage has at least one hysteresis feedback path from the second node for providing hysteresis in the response of the second signal to the first signal; and wherein the buffer presents a hysteresis that is smaller when the first and second buffer stages are both enabled than when the first buffer stage is enabled and the second buffer stage is disabled.
地址 Austin TX US