| 发明名称 |
Spacer Etching Process for Integrated Circuit Design |
| 摘要 |
A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a first patterning process; and forming a second plurality of trenches in the first layer by second patterning process, wherein a first trench of the second plurality merges with two trenches of the first plurality to form a continuous trench. The method further includes forming spacer features on sidewalls of the first and second pluralities of trenches. The spacer features have a thickness. A width of the first trench is equal to or less than twice the thickness of the spacer features thereby the spacer features merge inside the first trench. |
| 申请公布号 |
US2017069505(A1) |
申请公布日期 |
2017.03.09 |
| 申请号 |
US201615357203 |
申请日期 |
2016.11.21 |
| 申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
LIU RU-GUN;TSAI CHENG-HSIUNG;LEE CHUNG-JU;LAI CHIH-MING;LEE CHIA-YING;SHIEH JYU-HORNG;HSIEH KEN-HSIEN;SHIEH MING-FENG;SHUE SHAU-LIN;CHANG SHIH-MING;BAO TIEN-I;GAU TSAI-SHENG |
| 分类号 |
H01L21/308;H01L21/8234;H01L21/02;H01L21/311;H01L21/3105 |
主分类号 |
H01L21/308 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method, comprising:
forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a first patterning process; forming a second plurality of trenches in the first layer by a second patterning process, resulting in combined trench patterns in the first layer, wherein a first trench of the second plurality merges with two trenches of the first plurality to form a continuous trench; and forming spacer features on sidewalls of the combined trench patterns, the spacer features having a thickness, wherein a width of the first trench is equal to or less than twice the thickness of the spacer features, thereby the spacer features merge inside the first trench. |
| 地址 |
HSIN-CHU TW |
