Hardware Migration between Dissimilar Cores

摘要

In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. The processor may support multiple processor states (PStates). Each PState may specify an operating point (e.g. a combination of supply voltage magnitude and clock frequency), and each PState may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core. The context switch may be performed using a special purpose register (SPR) interconnect. Each processor core in a given processor may be coupled to the SPR interconnect to permit access to the external SPRs.

主权项

1. An apparatus comprising:
a processor having a plurality of power states comprising:
a first processor core, wherein a first subset of the plurality of power states map to the first processor core; anda second processor core, wherein a second subset of the plurality of power states map to the second processor core, and wherein the first subset and the second subset are non-overlapping; a special purpose register interconnect coupled to the first processor core and the second processor core, the special purpose register interconnect providing access to a plurality of special purpose registers; and a control circuit configured to control migration of processor state between the first processor core and the second processor core responsive to a change between a first processor state in the first subset and a second processor state in the second subset, wherein the control circuit is configured to cause transfer of register state from a source core of the first processor core and the second processor core to a target core of the first processor core and the second processor core over the special purpose register interconnect.