发明名称 |
TOP PINNED SOT-MRAM ARCHITECTURE WITH IN-STACK SELECTOR |
摘要 |
Embodiments of the present disclosure generally relate to data storage and computer memory systems, and more particularly, to a SOT-MRAM cell and chip architecture. The SOT-MRAM chip architecture includes a memory cell array having a plurality of first leads, a plurality of second leads, and a plurality of memory cells. Each memory cell of the plurality of memory cells includes a MTJ and a selector element. These SOT-MRAM cells eliminate the need to pass large currents through the barrier layer of the MTJ and the selector element eliminates the large transistors usually required for selecting a single memory cell without disturbing neighboring memory cells. |
申请公布号 |
US2017117027(A1) |
申请公布日期 |
2017.04.27 |
申请号 |
US201514919247 |
申请日期 |
2015.10.21 |
申请人 |
HGST Netherlands B.V. |
发明人 |
BRAGANCA Patrick M.;WAN Lei |
分类号 |
G11C11/16;H01L43/02;H01L43/08;H01L27/22 |
主分类号 |
G11C11/16 |
代理机构 |
|
代理人 |
|
主权项 |
1. A memory cell, comprising:
a magnetic tunnel junction; and a selector element disposed on the magnetic tunnel junction. |
地址 |
Amsterdam NL |