IMAGE PROCESSOR AND DISPLAY SYSTEM

摘要

An image processor includes a frame buffer configured to collect an image data of pixels and configured to generate frame data, a display controller configured to generate the frame update command based on a vertical synchronizing signal and a frame per second signal representing a number of activating of the frame update signal in a second and an operating part configured to generate the vertical synchronizing signal and the image data. When the frame data is generated, the frame buffer activates a frame update signal in response to a frame update command and outputs the frame data. When the frame per second signal is less than a predetermined threshold voltage, the operating part sets a lower limit of a range of a frequency to a predetermined minimum frequency.

主权项

1. An image processor comprising:
a frame buffer configured to collect image data of pixels and generate frame data, wherein when the frame data is generated, the frame buffer activates a frame update signal in response to a frame update command and outputs the frame data; a display controller configured to generate the frame update command based on a vertical synchronizing signal and a frame per second signal indicating a number per second of frame update signal activations; and an operating part configured to generate the vertical synchronizing signal and collect the image data, wherein when the frame per second signal is less than a predetermined threshold voltage, the operating part sets a lower limit of a range of a frequency to a predetermined minimum frequency.