| 摘要 |
A circuit can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with a common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a first input voltage Vinp, a reference voltage Vref, the common mode voltage Vcm, and ground; a second plurality of capacitors Cn[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with the common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a second input voltage Vinn, the reference voltage Vref, the common mode voltage Vcm, and ground; and a successive approximation register (SAR) controller coupled with the output of the voltage comparator Vd. |
| 主权项 |
1. A circuit, comprising:
a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with a common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a first input voltage Vinp, a reference voltage Vref, the common mode voltage Vcm, and ground; a second plurality of capacitors Cn[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with the common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a second input voltage Vinn, the reference voltage Vref, the common mode voltage Vcm, and ground, wherein the first and second pluralities of capacitors together represent multiple sections that include two most significant bits (MSBs) C[3] and C[7], each MSB having three corresponding least significant bits (LSBs) C[2:0] and C[6:4], respectively, and further wherein a bit weight of each of the most significant bits (MSBs) C[3] and C[7] is equal to a sum of bit weights of the corresponding least significant bits (LSBs) C[2]+C[1]+C[0] and C[6]+C[5]+C[4], respectively; and a successive approximation register (SAR) controller coupled with the output of the voltage comparator Vd. |
