发明名称 Systems And Methods For Binding Mismatched Schematic And Layout Design Hierarchy
摘要 Disclosed herein are systems and methods that allow a layout editor function, presented in a graphical user interface, of an EDA, to indicate certain layout instances or “cell views” as “transparent.” The instances are indicated as transparent using various layout editor commands or layout designer markers. Unlike conventional solutions, a binder within the layout editor of the EDA is not required to bind layout transparent instances to corresponding instances in a related schematic design file or records. Instead, the EDA may identify non-transparent instances at a lower-level of the layout design's hierarchy to bind, because the systems and methods described herein provide for a transparent instance container at a hierarchically higher-level.
申请公布号 US2017124235(A1) 申请公布日期 2017.05.04
申请号 US201514981422 申请日期 2015.12.28
申请人 CADENCE DESIGN SYSTEMS, INC. 发明人 Ferguson Kenneth;Bourguet Jean-Marc
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项 1. A computer-implemented method comprising: upon a computer detecting a change to an attribute of a layout instance in a record of the layout instance stored in a design database: identifying, by the computer, one or more attributes of the layout instance in the record of the layout instance, upon determining that a parent instance containing the layout instance is a transparent instance according to one or more attributes of the parent instance in a record of the parent instance;determining, by the computer, a likelihood the layout instance corresponds to a schematic instance; andgenerating, by the computer, a binding attribute in the one or more attributes of the layout instance indicating the layout instance corresponds to the schematic instance.
地址 SAN JOSE CA US
您可能感兴趣的专利