METHOD FOR MANUFACTURING ARRAY SUBSTRATE AND MANUFACTURING DEVICE

摘要

Embodiments of the present invention disclose a manufacturing method for an array substrate and corresponding manufacturing device, which belong to the technical field of metal oxide semiconductor. The method comprises: forming an active layer, a gate insulating layer and a gate metal layer successively on a substrate; forming a gate pattern with a gate photoresist pattern on the substrate having the gate metal layer; altering a temperature of the gate photoresist pattern, so as to enable the width of the gate photoresist sub-pattern in the gate photoresist pattern to be changed; forming lightly doped drains (LDDs) at two sides of a preset area of the active layer sub-pattern in the active layer of the substrate having the changed gate photoresist pattern, the preset area being a projection area of the gate sub-pattern on the active layer sub-pattern, the length of each of the LDDs being (a−b)/2, wherein a is the width of the gate photoresist sub-pattern in the changed gate photoresist pattern, b is the width of the gate sub-pattern; stripping the changed gate photoresist pattern. The embodiment of the present invention mitigates or alleviates the problem of relatively low control flexibility and relatively poor feasibility to the LDD length, which improves the control flexibility and feasibility to the LDD length, and can be used for manufacturing an array substrate.

主权项

1. A method for manufacturing an array substrate, wherein the method comprises:
forming an active layer, a gate insulating layer and a gate metal layer successively on a substrate, the active layer comprising a plurality of active layer sub-patterns; forming a gate pattern with a gate photoresist pattern on the substrate having the gate metal layer, the gate pattern comprising a plurality of gate sub-patterns formed from the gate metal layer, the gate photoresist pattern comprising a plurality of gate photoresist sub-patterns, the width of each gate photoresist sub-pattern in the gate photoresist pattern being greater than the width of each gate sub-pattern in the gate pattern; altering a temperature of the gate photoresist pattern, so as to enable the width of the gate photoresist sub-pattern in the gate photoresist pattern to be changed; forming lightly doped drains (LDDs) at two sides of a preset area of the active layer sub-pattern in the active layer of the substrate having the changed gate photoresist pattern, the preset area being a projection area of the gate sub-pattern on the active layer sub-pattern, the length of each LDD is (a−b)/2, wherein a is the width of the gate photoresist sub-pattern in the changed gate photoresist pattern, b is the width of the gate sub-pattern in the gate pattern; stripping the changed gate photoresist pattern.