SYSTEMS AND METHODS OF PIPELINED OUTPUT LATCHING INVOLVING SYNCHRONOUS MEMORY ARRAYS

摘要

Systems and methods of synchronous memories and synchronous memory operation are disclosed. According to one illustrative implementation, a memory device is disclosed comprising memory circuitry having a memory output, the memory circuitry including a sense amplifier having a first output and a second output, a first data path coupled to the first output of the sense amplifier, the first data path including 2 latches/registers, and a second data path coupled to the second output of the sense amplifier, the second data path including a plurality latches/registers. In further implementations, various control circuitry, connections and control signals may be utilized to operate the latches/registers in the first and second data paths according to specified configurations, control, modes, latency and/or timing domain information, to achieve, for example, pipelined output latching and/or double data rate output.

主权项

1. A synchronous memory device, comprising:
memory circuitry having a memory output (Q) and including:
a sense amplifier having a first output and a second output;a first data path (B1) coupled to the first output of the sense amplifier, the first data path having 2 latches/registers;a second data path (B2) coupled to the second output of the sense amplifier, the second data path having 3 latches/registers; wherein the first data path and the second data path are combined by output circuitry to provide a double data rate output; and wherein a first latch in the first data path has an input coupled to a sense amplifier tracking delay signal;