FULLY-DIGITAL FULLY-SYNTHESIZABLE DELAY-LINE ANALOG TO DIGITAL CONVERTER

摘要

The present invention relates to the realization of an ADC by using a one shot time cell as an analog-to-time converter and a time-to-digital converter. The present invention relates in general, to the design and Integrated Circuit (IC) implementation of a fully-digital fully-synthesizable, delay-line analog-to-digital converter (DL-ADC). The present invention is specifically relevant for power management applications where the silicon area of the controller is of key importance. The design of the ADC is based on the approach of delay cells string to reduce design complexity and the resultant of the silicon area.

主权项

1. An analog to digital converter which comprises:
a) an analog to time converter being a one shot time cell, which receives as an input a pulse trigger signal and outputs a pulse signal Vx, wherein the duration of Vx is proportional to the voltage levels and/or to the components in said one shot time cell, that determine the time response of said one shot time cell; and b) a time to digital converter, which receives said output pulse signal Vx as an input and outputs a digital representation of the duration of said Vx signal.