发明名称 PREDICTIVE SIGMA-DELTA ADC FILTER
摘要 A sigma-delta analog-to-digital converter comprises a sigma-delta modulator; and an ADC filter that receives a segment of L binary samples from the sigma-delta modulator, L being a positive integer. The ADC filter includes a predictor circuit that determines whether a power consumption of a first summing method would be higher than a power consumption of a second summing method, based on a content of the segment, and an accumulator circuit that calculates an output using the first summing method in a case where the power consumption of the first summing method would be lower than the power consumption of the second summing method, and using the second summing method in a case where the power consumption of the first summing method would be higher than the power consumption of the second summing method.
申请公布号 US2017126245(A1) 申请公布日期 2017.05.04
申请号 US201514928486 申请日期 2015.10.30
申请人 Sony Semiconductor Solutions Corporation 发明人 Shem Ariel Ben;Shvartz Itai
分类号 H03M3/00;H01L27/146 主分类号 H03M3/00
代理机构 代理人
主权项 1. A sigma-delta analog-to-digital converter, comprising: a sigma-delta modulator; and an ADC filter configured to receive a segment of L binary samples from the sigma-delta modulator, L being a positive integer, including: a predictor circuit configured to determine whether a power consumption of a first summing method would be higher than a power consumption of a second summing method, based on a content of the segment, andan accumulator circuit configured to calculate an output using the first summing method in a case where the power consumption of the first summing method would be lower than the power consumption of the second summing method, and using the second summing method in a case where the power consumption of the first summing method would be higher than the power consumption of the second summing method.
地址 Kanagawa JP