发明名称 Organizing Memory to Optimize Memory Accesses of Compressed Data
摘要 In one embodiment of the present invention a cache unit organizes data stored in an attached memory to optimize accesses to compressed data. In operation, the cache unit introduces a layer of indirection between a physical address associated with a memory access request and groups of blocks in the attached memory. The layer of indirection—virtual tiles—enables the cache unit to selectively store compressed data that would conventionally be stored in separate physical tiles included in a group of blocks in a single physical tile. Because the cache unit stores compressed data associated with multiple physical tiles in a single physical tile and, more specifically, in adjacent locations within the single physical tile, the cache unit coalesces the compressed data into contiguous blocks. Subsequently, upon performing a read operation, the cache unit may retrieve the compressed data conventionally associated with separate physical tiles in a single read operation.
申请公布号 US2017123977(A1) 申请公布日期 2017.05.04
申请号 US201514925920 申请日期 2015.10.28
申请人 NVIDIA CORPORATION 发明人 KRISHNAMURTHY Praveen;HOLMQUIST Peter B.;GANDHI Wishwesh;PURCELL Timothy;MEHRA Karan;SHAH Lacky
分类号 G06F12/08;G06F3/06 主分类号 G06F12/08
代理机构 代理人
主权项 1. A system configured to process memory accesses associated with compressed data, the system comprising: a processor; and a cache memory coupled to the processor and configured to: receive a first memory access request from the processor to write first compressed data to a first physical address within another memory;in response, select a first group of blocks within the another memory based on the first physical address;determine that a first storage state associated with the first group of blocks indicates that a first physical tile included in the first group of blocks already stores second compressed data; andstore the first compressed data adjacent to the second compressed data in the first physical tile.
地址 Santa Clara CA US