| 发明名称 |
INSTRUCTION FUSION |
| 摘要 |
An apparatus includes a processing pipeline comprising a plurality of stages, the plurality of stages including at least one instruction fusing stage to detect whether a block of instructions to be processed comprises a fusible group of instructions, and to generate a fused instruction to be processed by a subsequent stage of the processing pipeline when said block of instructions comprises said fusible group. However, when said block of instructions comprises a partial subset of said fusible group of instructions, the instruction fusing stage is configured to delay handling of said partial subset of said fusible group of instructions until the instruction fusing stage has determined whether at least one subsequent block of instructions to be processed comprises a remaining subset of instructions of said fusible group. |
| 申请公布号 |
US2017123808(A1) |
申请公布日期 |
2017.05.04 |
| 申请号 |
US201514929904 |
申请日期 |
2015.11.02 |
| 申请人 |
ARM Limited |
发明人 |
CAULFIELD Ian Michael;PATHIRANE Chiloda Ashan Senerath |
| 分类号 |
G06F9/38;G06F9/30 |
主分类号 |
G06F9/38 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus comprising:
a processing pipeline comprising a plurality of stages;
the plurality of stages comprising at least one instruction fusing stage to detect whether a block of instructions to be processed comprises a fusible group of instructions, and to generate a fused instruction to be processed by a subsequent stage of the processing pipeline when said block of instructions comprises said fusible group;wherein when said block of instructions comprises a partial subset of said fusible group of instructions, the instruction fusing stage is configured to delay handling of said partial subset of said fusible group of instructions until the instruction fusing stage has determined whether at least one subsequent block of instructions to be processed comprises a remaining subset of instructions of said fusible group. |
| 地址 |
Cambridge GB |
