Reference-less Frequency Detector With High Jitter Tolerance

摘要

An apparatus, comprising a first sampling circuit configured to sample a clock signal according to a data signal to produce a first sampled signal, a second sampling circuit configured to sample the clock signal according to a delay signal to produce a second sampled signal, and a control circuit coupled to the first sampling circuit and the second sampling circuit, wherein the control circuit is configured to perform a not-and (NAND) operation according to the first sampled signal and the second sampled signal to produce an activation signal for activating a frequency adjustment for the clock signal.

主权项

1. An apparatus comprising:
a not-and (NAND) gate comprising a first NAND gate input port, a second NAND gate input port, and a NAND gate output port; and a voltage-to-current (V2I) converter comprising a V2I converter activation port and a V2I converter output current port, wherein the V2I converter activation port is coupled to the NAND gate output port, and wherein the V2I converter output current port is configured to couple to a frequency detection loop filter.