发明名称 |
INTEGRATED CIRCUIT STRUCTURE AND METHOD OF FORMING THE SAME |
摘要 |
An integrated circuit structure with a back side through silicon via (B/S TSV) therein and a method of forming the same is disclosed. The method includes the steps of: receiving a wafer comprising a substrate having a front side that has a conductor thereon and a back side; forming a back side through silicon via (B/S TSV) from the back side of the substrate to penetrate the substrate; and filling the back side through silicon via (B/S TSV) with a conductive material to form an electrical connection with the conductor. Thus a back side through silicon via penetrates the back side of the substrate and electrically connects to the conductor on the front side of the substrate is formed. |
申请公布号 |
US2017125341(A1) |
申请公布日期 |
2017.05.04 |
申请号 |
US201514929040 |
申请日期 |
2015.10.30 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
LIN Jeng-Shyan;YAUNG Dun-Nian;LIN Hsing-Chih;LIU Jen-Cheng;KAO Min-Feng;HUANG Hsun-Ying |
分类号 |
H01L23/522;H01L21/768;H01L23/528 |
主分类号 |
H01L23/522 |
代理机构 |
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代理人 |
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主权项 |
1. A method of forming an integrated circuit structure, the method comprising:
receiving a substrate having a front side that comprises a conductor thereon and a back side; thinning down the substrate from the back side of the substrate; forming a first photo resist mask to etch a first via hole from the back side of the substrate without exposing the conductor; forming a side wall film on a side wall of the first via hole without covering a bottom of the first via hole; forming a second photo resist mask to etch through the bottom of the first via hole to form a second via hole, which has a size smaller than a size of the first via hole, to expose the conductor; and filling the first and second via holes with a conductive material to be electrically connected to the conductor. |
地址 |
HSINCHU TW |