发明名称 LOGIC DIE AND OTHER COMPONENTS EMBEDDED IN BUILD-UP LAYERS
摘要 Embodiments of the present disclosure are directed towards package assemblies, as well as methods for forming package assemblies and systems incorporating package assemblies. A package assembly may include a substrate including a plurality of build-up layers, such as bumpless build-up layer (BBUL). In various embodiments, electrical routing features may be disposed on an outer surface of the substrate. In various embodiments, a primary logic die and a second die or capacitor may be embedded in the plurality of build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power or a ground signal between the second die or capacitor and the electrical routing features, bypassing the primary logic die.
申请公布号 US2017125351(A1) 申请公布日期 2017.05.04
申请号 US201615346568 申请日期 2016.11.08
申请人 INTEL CORPORATION 发明人 Kulkarni Deepak V.;Mortensen Russell K.;Guzek John S.
分类号 H01L23/538;H01L49/02;H01L21/768;H01L23/48;H01L21/48 主分类号 H01L23/538
代理机构 代理人
主权项
地址 SANTA CLARA CA US