TEST LINE STRUCTURE AND METHOD FOR PERFORMING WAFER ACCEPTANCE TEST

摘要

Test line structures on a wafer are provided. A first testing pad is formed in a scribe line of the wafer. A second testing pad is formed in the scribe line. A transistor under test is formed in the scribe line and is coupled between the first testing pad and the second testing pad. A device is formed in the scribe line and is coupled between the first testing pad and the transistor under test. A third testing pad is formed in the scribe line and is coupled between the device and the transistor under test. A current passing through the transistor under test is measured via the second testing pad or the first testing pad when a first voltage is applied to the first testing pad, wherein the first voltage is determined according to a second voltage from the third testing pad.

主权项

1. A test line structure on a wafer, comprising:
a first testing pad formed in a scribe line of the wafer; a second testing pad formed in the scribe line; a transistor under test formed in the scribe line and coupled between the first testing pad and the second testing pad; a device formed in the scribe line and coupled between the first testing pad and the transistor under test; and a third testing pad formed in the scribe line and coupled between the device and the transistor under test, wherein a current passing through the transistor under test is measured via the second testing pad or the first testing pad when a first voltage is applied to the first testing pad, wherein the first voltage is determined according to a second voltage from the third testing pad.